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w39v040a 512k 8 cmos flash memory with lpc interface publication release date: december 19, 2002 - 1 - revision a2 1. general description the w39v040a is a 4-megabit, 3.3-volt only cmos flash memory organized as 512k 8 bits. for flexible erase capability, the 4mbits of data are divided into 8 unifo rm sectors of 64 kbytes, which are composed of 16 smaller even pages with 4 kbyt es. the device can be programmed and erased in-system with a standard 3.3v power supply. a 12-volt v pp is not required. the unique cell architecture of the w39v040a results in fast pr ogram/erase operations with extrem ely low current consumption. this device can operate at two modes, programmer bus interface mode and lpc bus interface mode. as in the programmer interface mode, it acts like the tradi tional flash but with a multiplexed address inputs. but in the lpc interface mode, this device complies with the intel lpc specification. the device can also be programmed and erased using standard eprom programmers. 2. features ? single 3.3-volt operations: ? 3.3-volt read ? 3.3-volt erase ? 3.3-volt program ? fast program operation: ? byte-by-byte programming: 35 s (typ.) ? fast erase operation: ? chip erase 100 ms (max.) ? sector erase 25 ms (max.) ? page erase 25 ms (max.) ? fast read access time: tkq 11 ns ? endurance: 10k cycles (typ.) ? twenty-year data retention ? 8 even sectors with 64k bytes each, which is composed of 16 flexible pages with 4k bytes ? any individual sector or page can be erased ? hardware protection: ? optional 16k byte or 64k byte top boot block with lockout protection ? #tbl & #wp support the whole chip hardware protection ? flexible 4k-page size can be used as parameter blocks ? low power consumption ? active current: 12.5 ma (typ. for lpc mode) ? automatic program and erase timing with internal v pp generation ? end of program or erase detection ? toggle bit ? data polling ? latched address and data ? ttl compatible i/o ? available packages: 32l plcc, 32l stsop
w39v040a - 2 - 3. pin configurations 5 6 7 9 10 11 12 13 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 20 19 18 17 16 15 14 d q 1 ^ l a d 1 v v s s d q 6 ^ r s v v # r e s e t v d d r / # c ^ c l k v a 9 ^ g p i 3 v 32l plcc a 1 0 ^ g p i 4 v n c dq0(lad0) a7(gpi1) a6(gpi0) a3(rsv) a2(rsv) a1(rsv) a0(rsv) mode dq7(rsv) #we(#lfram) #oe(#init) nc vss a 8 ^ g p i 2 v d q 2 ^ l a d 2 v d q 3 ^ l a d 3 v d q 4 ^ r s v v d q 5 ^ r s v v nc v dd a4(#tbl) a5(#wp) nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32l stsop 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a9(gpi3) #reset nc a8(gpi2) a7(gpi1) a6(gpi0) v dd mode nc a10(gpi4) r/#c(clk) dq0(lad0) a3(rsv) a2(rsv) a1(rsv) a0(rsv) dq1(lad1) dq2(lad2) dq6(rsv) dq5(rsv) dq4(rsv) dq3(lad3) dq7(rsv) #we(#lfra m #oe(#init) v v ss a4(#tbl) a5(#wp) v ss dd nc nc 4. block diagram program- mer interface 7ffff 00000 boot block, 16k bytes 60000 5ffff 7c000 7bfff 40000 3ffff parameter block1, 8k bytes parameter block2, 8k bytes 7a000 79fff 78000 77fff #reset lpc interface mode clk #lfram lad[3:0] a[10:0] dq[7:0] #oe #we r/#c 70000 6ffff main memory sector3, 64k bytes main memory sector2, 64k bytes main memory sector1, 64k bytes main memory sector0, 64k bytes 20000 1ffff 50000 4ffff 30000 2ffff 10000 0ffff main memory sector4, 64k bytes main memory sector5, 64k bytes main memory sector6, 64k bytes memory block, 32k bytes main memory sector7, 64k bytes #tbl #wp 5. pin description interface sym. pgm lpc pin name mode * * interface mode selection #reset * * reset #init * initialize #tbl * top boot block lock #wp * write protect clk * clk input gpi[4:0] * general purpose inputs id[3:0] * identification inputs lad[3:0] * addr ess/data inputs #lfram * lpc cycle initial r/ #c * row/column select a[10:0] * address inputs dq[7:0] * data inputs/outputs #oe * output enable #we * write enable v dd * * power supply v ss * * ground rsv * * reserve pins nc * * no connection
w39v040a publication release date: december 19, 2002 - 3 - revision a2 6. functional description interface mode selection and description this device can be operated in two interface modes, one is programmer interface mode, and the other is lpc interface mode. the mode pin of the device provides the control between these two interface modes. these interface modes need to be configured before po wer up or return from #reset . when mode pin is set to high position, the device is in the programmer mode; while the mode pin is set to low position, it is in the lpc mode. in programmer mode, this device just behaves like traditional flash parts with 8 data lines. but the row and column ad dress inputs are multiple xed. the row address is mapped to the higher internal address a[18:11]. and the column address is mapped to the lower internal address a[10:0]. for lpc mode, it complies with the lp c interface specification revision 1.0. through the lad[3:0] and #lfram to communicate with the system chipset . read(write) mode in programmer interface mode, the read(write) operati on of the w39v040a is controlled by #oe (#we). the #oe (#we) is held low for the host to obtain(wr ite) data from(to) the outputs(inputs). #oe is the output control and is used to gate data from the out put pins. the data bus is in high impedance state when #oe is high. as in the lpc interface the "b it 1 of cycle type+dir" determines mode, the read or write. refer to the timing waveforms for further details. reset operation the #reset input pin can be used in some application. when #reset pin is at high state, the device is in normal operation mode. when #reset pin is at lo w state, it will halt the device and all outputs will be at high impedance state. as the hi gh state re-asserted to the #reset pi n, the device will return to read or standby mode, it depends on the control signals. boot block operation and hardware protection at initial - #tbl and #wp there are two alternatives to set t he boot block. either 16k-byte or 64k -byte in the top location of this device can be locked as boot block, which can be used to store boot codes. it is located in the last 16k/64k bytes of the memory with the addr ess range from 7c000(hex)/70000(hex) to 7ffff(hex). see command codes for boot block lockout enable for the specific code. once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method. besides the software method, there is a hardwar e method to protect the top boot block and other sectors. before power on programmer, tie the #tbl pin to low state and then the top boot block will not be programmed/erased. if #wp pin is tied to low state before powe r on, the other sectors will not be programmed/erased. in order to detect whether the boot block feature is set on or not, users can perform software command sequence: enter the product identification mode (s ee command codes for identification/boot block lockout detection for specific code), and then read from address 7fff2(hex). if the dq0/dq1 output data is "1," the 64kbytes/16kbytes boot block programming lockout f eature will be activated; if the dq0/dq1 output data is "0," the lockout feat ure will be inactivated and the boot block can be erased/programmed. but the hardware protection will override the software lock setting, i.e., while the #tbl pin is trapped at low state, the top boot bloc k cannot be programmed/erased whether the output data, dq0/dq1 at the address 7fff2, is "0" or "1". the #tbl will lock the whole 64kbytes top boot
w39v040a - 4 - block, it will not partially lock the 16kbytes boot block. you can check the dq2/dq3 at the address 7fff2 to see whether the #tbl/#wp pin is in low or high state. if the dq2 is "0", it means the #tbl pin is tied to high state. in such condition, whether boot block can be programmed/erased or not will depend on software setting. on the other hand, if the dq2 is "1", it means the #tbl pin is tied to low state, then boot block is locked no matter how the software is se t. like the dq2, the dq3 inversely mirrors the #wp state. if the dq3 is "0", it means the #wp pin is in high state, then all t he sectors except the boot block can be programmed/erased. on the other hand, if th e dq3 is "1", then all the sectors except the boot block are programmed/erased inhibited. to return to normal operation, perform a three-by te command sequence (or an alternate single-byte command) to exit the identification mode. fo r the specific code, see command codes for identification/boot blo ck lockout detection. chip erase operation the chip-erase mode can be initiated by a six- byte command sequence. after the command loading cycle, the device enters the internal chip erase mo de, which is automatically timed and will be completed within fast 100 ms (max). the host system is not required to provide any control or timing during this operation. if the boot block programming lockout is ac tivated, only the data in the other memory sectors will be erased to ff(hex) while the data in the boot bl ock will not be erased (remains as the same state before the chip erase operation). the entire memory array will be erased to ff(hex) by the chip erase operation if the ?boot block programm ing lockout feature? is not activa ted. the device will automatically return to normal read mode after the erase operation completed. data polling and/or toggle bits can be used to detect end of erase cycle. sector/page erase operation sector/page erase is a six-bus cycles operation. there are two "unlock" write cycles, followed by writing the "set-up" command. two more "unlock" write cy cles then follows by the sector/page erase command. the sector/page address (any address location within the desired sector/page) is latched on the rising edge of r/c, while the command (30h/50h) is latched on the rising edge of #we in programmer mode. sector/page erase does not require the user to program the device prior to erase. when erasing a sector/page or sectors/pages the remaining unselect ed sectors/pages are not a ffected. the system is not required to provide any controls or timings during these operations. the automatic sector/page erase begins after the er ase command is completed, right from the rising edge of the #we pulse for the last sector/page er ase command pulse and terminates when the data on dq7, data polling, is "1" at which time the devic e returns to the read mode. data polling must be performed at an address within any of the sectors/pages being erased. refer to the erase command flow chart usi ng typical command strings and bus operations. program operation the w39v040a is programmed on a byte-by-byte basis. program operation can only change logical data "1" to logical data "0." the erase operation, wh ich changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. the program operation is initiated by a 4-byte command cycle (see command codes for byte programming). the device will internally enter the program operation immediately after the byte-program command is entered. the internal program timer will automatically time-out (50 s max. - t bp ) once it is completed and then return to normal read mode. data polling and/or toggle bits can be used to detect end of program cycle.
w39v040a publication release date: december 19, 2002 - 5 - revision a2 hardware data protection the integrity of the data stored in the w39v040a is also hardware protected in the following ways: (1) noise/glitch protection: a #we pulse of less than 15 ns in duration will not initiate a write cycle. (2) v dd power up/down detection: the programming and read operation is inhibited when v dd is less than 1.5v typical. (3) write inhibit mode: forcing #oe low or #we high will inhibit the write operation. this prevents inadvertent writes during pow er-up or power-down periods. (4) v dd power-on delay: when v dd has reached its sense level, the de vices will automatically time-out 5 ms before any write (erase/program) operation. data polling (dq 7 )- write status detection the w39v040a includes a data polling feature to indica te the end of a program or erase cycle. when the w39v040a is in the internal program or erase cycle, any attempts to read dq 7 of the last byte loaded will receive the complement of the true data. once the program or erase cycle is completed, dq 7 will show the true data. note that dq 7 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed. toggle bit (dq 6 )- write status detection in addition to data polling, the w39v040a provid es another method for determining the end of a program cycle. during the internal program or er ase cycle, any consecutive attempts to read dq 6 will produce alternating 0's and 1's. when the program or erase cycle is completed, this toggling between 0's and 1's will stop. the device is then ready for the next operation. multi-chip operation multiple devices can be wired on the single lpc bus. there are four id pins can be used to support up to 16 devices. but in order not to violate the bios rom memory space defined by intel, winbond w39v040a will only used 3 id pins to allow up to 8 devices, 4mbytes for bios code and 4mbytes for registers memory space. register there are two kinds of re gisters on this device, the general purpose input registers and product identification registers. users can access these registers through respective address in the 4gbytes memory map. there are detail descriptions in the sections below. general purpose inputs register this register reads the states of gpi[4:0] pins on the w39v040a. this is a pass-through register, which can be read via memory address ffbxe 100(hex). the "x" in the addresse s represents the id [3:0] pin straps. since it is pass-through r egister, there is no default value.
w39v040a - 6 - gpi register bit function 7 ? 5 reserved 4 read gpi4 pin status 3 read gpi3 pin status 2 read gpi2 pin status 1 read gpi1 pin status 0 read gpi0 pin status product identification registers there is an alternative software method (six command s bytes) to read out the product identification in both the programmer interface mode and the lpc interface mode. thus, the programming equipment can automatically matches the device with its proper erase and programming algorithms. in the software access mode, a six-byte (or jede c 3-byte) command sequence can be used to access the product id for programmer interface mode. a read from address 0000(hex) outputs the manufacturer code, da(hex). a read from addres s 0001(hex) outputs the devic e code, 3d(hex).? the product id operation can be terminated by a thr ee-byte command sequence or an alternate one-byte command sequence (see command definition table for detail). identification input pins id[3:0] these pins are part of mechanism that allows multiple parts to be used on the same bus. the boot device should be 0000b. and all the subsequent parts sh ould use the up-count strapping. note that a 1m byte rom will occupy two ids. for example: a 1mby te rom's id is 0000b, the next rom's id is 0010b. these pins all are pulled down with internal resistor. memory address map there are 8m bytes space reserved for bios addressing. the 8m by tes are mapped into a single 4m system address by dividing the roms into two 4m byte pages. for accessing the 4m byte bios storage space, the id[2:0] pins are inverted in the rom and are compared to address lines [21:19]. id[3] can be used as like active low chip-select pin. the 32mbit address space is as below: block lock address range 4m byte bios rom none ffff, ffffh: ffc0, 0000h the rom responds to 640k (top 512k + bottom 128k ) byte pages based on the id pins strapping according to the following table: id[2:0] pins rom based address range 000 ffff, ffffh: fff8, 0000h & 000f, ffffh: 000e, 00000h 001 fff7, ffffh: fff0, 0000h 010 ffef, ffffh: ffe8, 0000h 011 ffe7, ffffh: ffe0, 0000h
w39v040a publication release date: december 19, 2002 - 7 - revision a2 continued 100 ffdf, ffffh: ffd8, 0000h 101 ffd7, ffffh: ffd0, 0000h 110 ffcf, ffffh: ffc8, 0000h 111 ffc7, ffffh: ffc0, 0000h table of operating modes operating mode selection - programmer mode pins mode #oe #we #reset address dq. read v il v ih v ih ain dout write v ih v il v ih ain din standby x x v il x high z v il x v ih x high z/dout write inhibit x v ih v ih x high z/dout output disable v ih x v ih x high z operating mode selection - lpc mode operation modes in lpc interface mode are determined by "cycle type" when it is selected. when it is not selected, its outputs (lad[3:0]) will be disabl e. please reference to the "standard lpc memory cycle definition". standard lpc memory cycle definition field no. of clocks description start 1 "0000b" appears on lpc bus to indicate the initial cycle type & dir 1 "010xb" indicates memory read cycle; while "011xb" indicates memory write cycle. "x" mean don't have to care. tar 2 turned around time addr. 8 address phase for memory cycle. lpc supports the 32 bits address protocol. the addresses transfer most significant nibble first and least significant nibble last. (i.e. address[31:28] on lad[3:0] first , and addre ss[3:0] on lad[3:0] last.) sync. n synchronous to add wait state. " 0000b" means ready, "0101b" means short wait, "0110b" means long wait, "1001b" for dma only, "1010b" means error, other values are reserved. data 2 data phase for memory cycle. the data transfer least significant nibble first and most significant nibble last. (i.e. d q[3:0] on lad[3:0] first , then dq[7:4] on lad[3:0] last.)
w39v040a - 8 - table of command definition command no. of 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle description cycles addr. data addr. data addr . data addr. data addr. data addr. data read 1 a in d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (3) 30 page erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 pa (4) 50 byte program 4 5555 aa 2aaa 55 5555 a0 a in d in top boot block lockout ? 64k/16kbyte 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40/70 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (1) 3 5555 aa 2aaa 55 5555 f0 product id exit (1) 1 xxxx f0 notes: 1. the cycle means the write command cycle not the lpc clock cycle. 2. the column address / row address are mapped to the low / high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[7:0] are mapped to the internal a[18:11] 3. address format: a14 ? a0 (hex); data format: dq7 ? dq0 (hex) 4. either one of the two product id exit commands can be used. 5. sa: sector address sa = 7xxxxh for unique sector7 (boot secto r) sa = 3 xxxxh fo r unique sector3 sa = 6xxxxh for unique sector6 sa = 2xxxxh fo r unique sector2 sa = 5xxxxh for unique sector5 sa = 1xxxxh fo r unique sector1 sa = 4xxxxh for unique sector4 sa = 0xxxxh fo r unique sector0 6. pa: page address pa = 7fxxxh for page 15 in sector 7 pa = 7exxxh for page 14 in sector 7 pa = 7dxxxh for page 13 in sector 7 pa = 7cxxxh for page 12 in sector 7 pa = 7bxxxh for page 11 in sector 7 pa = 7axxxh for page 10 in sector 7 pa = 79xxxh for page 9 in sector 7 pa = 78xxxh for page 8 in sector 7 pa = 77xxxh for page 7 in sector 7 pa = 76xxxh for page 6 in sector 7 pa = 75xxxh for page 5 in sector 7 pa = 74xxxh for page 4 in sector 7 pa = 73xxxh for page 3 in sector 7 pa = 72xxxh for page 2 in sector 7 pa = 71xxxh for page 1 in sector 7 pa = 70xxxh for page 0 in sector 7 pa = 6fxxxh to 60xxxh for page 15 to page 0 in sector 6 (reference to the first column) pa = 5fxxxh to 50xxxh for page 15 to page 0 in sector 5 (reference to the first column) pa = 4fxxxh to 40xxxh for page 15 to page 0 in sector 4 (reference to the first column) pa = 3fxxxh to 30xxxh for page 15 to page 0 in sector 3 (reference to the first column) pa = 2fxxxh to 20xxxh for page 15 to page 0 in sector 2 (reference to the firs column) pa = 1fxxxh to 10xxxh for page 15 to page 0 in sector 1 (reference to the first column) pa = 0fxxxh to 00xxxh for page 15 to page 0 in sector 0 (reference to the first column)
w39v040a publication release date: december 19, 2002 - 9 - revision a2 embedded programming algorithm start write program command sequence (see below) increment address programming completed 5555h/aah 2aaah/55h 5555h/a0h program address/program data #data polling/ toggle bit last address ? no yes program command sequence (address/command): pause t bp
w39v040a - 10 - embedded erase algorithm start write erase command sequence (see below) erasure completed #data polling or toggle bit successfully completed 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h 5555h/10h chip erase command sequence (address/command): 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h sector address/30h (address/command): 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h pageaddress/50h individual page erase (address/command): individual sector erase command sequence command sequence pause t ec /t sec /t pec
w39v040a publication release date: december 19, 2002 - 11 - revision a2 embedded #data polling algorithm start read byte (dq0 - dq7) address = va pass dq7 = data ? yes no va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = any of the page addresses within the sector being erased during page erase operation = any of the device addresses within the chip being erased during chip erase operation embedded toggle bit algorithm start read byte (dq0 - dq7) address = don't care dq6 = toggle ? yes no fail
w39v040a - 12 - software product identification and boot block lockout detection acquisition flow product identification entry (1) load data 55 to address 2aaa load data 90 to address 5555 pause 10 s product identification and boot block lockout detection mode (3) read address = 00000 data = da read address = 00001 data = 3d read address = 00002 dq0/dq1 of data outputs = 1/0 (4) product identification exit (6) load data 55 to address 2aaa load data f0 to address 5555 normal mode (5) (2) (2) load data aa to address 5555 load data aa to address 5555 pause 10 s notes for software product identification/boot block lockout detection: (1) data format: dq7 ? dq0 (hex); address format: a14 ? a0 (hex) (2) a1 ? a18 = v il ; manufacture code is read for a0 = v il ; device code is read for a0 = v ih . (3) the device does not remain in ?identification and boot block lockout detection? mode if power down. (4) the dq[3:0] to indicate the sectors protect status as below: dq0 dq1 dq2 dq3 0 64kbytes boot block unlocked by software 16kbytes boot block unlocked by software 64kbytes boot block unlocked by #tbl hardware trapping whole chip unlocked by #wp hardware trapping except boot block 1 64kbytes boot block locked by software 16kbytes boot block locked by software 64kbytes boot block locked by #tbl hardware trapping whole chip locked by #wp hardware trapping except boot block (5) the device returns to standard operation mode. (6) optional 1-write cycle (write f0 hex at xxxx address) can be used to exit the ?product identification/boot block lockout detection.?
w39v040a publication release date: december 19, 2002 - 13 - revision a2 boot block lockout enable acquisition flow boot block lockout feature set flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40/70 to address 5555 exit 40 to lock 64k boot block 70 to lcok 16k boot block pause t bp
w39v040a - 14 - 7. dc characteristics absolute maximum ratings parameter rating unit power supply voltage to v ss potential -0.5 to +4.6 v operating temperature 0 to +70 c storage temperature -65 to +150 c d.c. voltage on any pin to ground potential -0.5 to v dd +0.5 v transient voltage (<20 ns) on any pin to ground potential -1.0 to v dd +0.5 v note: exposure to conditions beyond those listed under absolute ma ximum ratings may adversely affect the life and reliability of the device. programmer interface mode dc operating characteristics (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) limits parameter sym. test conditions min. typ. max. unit power supply current i cc in read or write mode, all dqs open address inputs = 3.0v/0v, at f = 3 mhz - 10 20 ma input leakage current i li v in = v ss to v dd - - 90 a output leakage current i lo v out = v ss to v dd - - 90 a input low voltage v il - -0.3 - 0.8 v input high voltage v ih - 2.0 - v dd +0.5 v output low voltage v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = -0.1ma 2.4 - - v
w39v040a publication release date: december 19, 2002 - 15 - revision a2 lpc interface mode dc operating characteristics (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) limits parameter sym. test conditions min. typ. max. unit power supply current i cc all i out = 0a, clk = 33 mhz, in lpc mode operation. - 12.5 20 ma cmos standby current isb1 #lfram = 0.9 v dd , clk = 33 mhz, all inputs = 0.9 v dd / 0.1 v dd - 5 25 a ttl standby current isb2 #lfram = 0.1 v dd , clk = 33 mhz, all inputs = 0.9 v dd / 0.1 v dd - 3 10 ma input low voltage v il - -0.5 - 0.3 v dd v input low voltage of #init pin v ili - -0.5 - 0.2 v dd v input high voltage v ih - 0.5 v dd - v dd + 0.5 v input high voltage of #init pin v ihi - 1.35v - v dd + 0.5 v output low voltage v ol1 i ol = 1.5 ma - - 0.1 v dd v output high voltage v oh1 i oh = -0.5 ma 0.9 v dd - v dd v power-up timing parameter symbol typical unit power-up to read operation t pu . read 100 s power-up to write operation t pu . write 5 ms capacitance (v dd = 3.3v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit i/o pin capacitance c i/o v i/o = 0v 12 pf input capacitance c in v in = 0v 6 pf
w39v040a - 16 - 8. programmer interface mode ac characteristics ac test conditions parameter conditions input pulse levels 0v to 0.9 v dd input rise/fall time < 5 ns input/output timing level 1.5v/1.5v output load 1 ttl gate and c l = 30 pf ac test load and waveform +3.3v 1.8k 1.3k d out ? ? 30 pf (including jig and scope) input 0.9vdd 0v test point test point 1.5v 1.5v output
w39v040a publication release date: december 19, 2002 - 17 - revision a2 ac characteristics read cycle timing parameters (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) w39v040a parameter symbol min. max. unit read cycle time t rc 300 - ns row/column address set up time t as 50 - ns row/column address hold time t ah 50 - ns address access time t aa - 175 ns output enable access time t oe - 75 ns #oe low to act output t olz 0 - ns #oe high to high-z output t ohz - 35 ns output hold from address change t oh 0 - ns write cycle timing parameters parameter symbol min. typ. max. unit reset time t rst 1 - - s address setup time t as 50 - - ns address hold time t ah 50 - - ns r/#c to write enable high time t cwh 50 - - ns #we pulse width t wp 100 - - ns #we high width t wph 100 - - ns data setup time t ds 50 - - ns data hold time t dh 50 - - ns #oe hold time t oeh 0 - - ns byte programming time t bp - 35 50 s sector/page erase cycle time t pec - 20 25 ms chip erase cycle time t ec - 75 100 ms note: all ac timing signals observe the following guide lines for determining setup and hold times: (a) high level signal's reference level is input high and (b) low level signal's reference level is input low. ref. to the ac testing condition. data polling and toggle bit timing parameters w39v040a parameter symbol min. max. unit #oe to data polling output delay t oep - 40 ns #oe to toggle bit output delay t oet - 40 ns
w39v040a - 18 - 9. timing waveforms for programmer interface mode read cycle timing diagram dq[7:0] high-z #oe #we v ih t oh t aa data valid t ohz high-z t olz t oe #reset a[10:0] t rc r/#c t as t ah row address column address t as t ah column address row address t rst write cycle timing diagram data valid t cwh t oeh t wp t ds t as t ah t wph t dh dq[7:0] #oe #we r/#c #reset a[10:0] column address row address t rst t as t ah
w39v040a publication release date: december 19, 2002 - 19 - revision a2 timing waveforms for programmer interface mode, continued program cycle timing diagram a[10:0] byte 0 byte 1 byte 2 internal write start dq[7:0] byte program cycle t bp t wph t wp 5555 5555 2aaa aa a0 55 programmed address data-in byte 3 note: the internal address a[18:0] are converted from external column/row addres s column/row address are mapped to the low/high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[7:0] are mapped to the internal a[18:11]. (internal a[18:0]) #oe #we r/#c #data polling timing diagram a[10:0] dq7 x x x t oep t ec t bp or x (internal a[18:0]) an an an an #oe #we r/#c
w39v040a - 20 - timing waveforms for programmer interface mode, continued toggle bit timing diagram a[10:0] dq6 t oet t ec t bp or #oe #we r/#c boot block lockout enable timing diagram sb2 sb1 sb0 dq[7:0] #oe #we sb3 sb4 sb5 t wp t wph aa 55 80 40/70 aa 55 note: the internal address a[18:0] are converted from external column/row address. column/row address are mapped to the low/high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[7:0] are mapped to the internal a[18:11]. (internal a[18:0]) six-byte code for boot block lockout command 5555 2aaa 5555 5555 2aaa 5555 a[10:0] r/#c t wc when 40(hex) is loaded, the 64kbyte are locked; while 70(hex) is loaded, the 16kbyte is locked.
w39v040a publication release date: december 19, 2002 - 21 - revision a2 timing waveforms for programmer interface mode, continued chip erase diagram dq[7:0] aa 55 80 aa 55 10 sb2 sb1 sb0 sb3 sb4 sb5 internal erasure starts t wp t wph t ec note: the internal address a[18:0] are converted from external column/row address. column/row address are mapped to the low/high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[7:0] are mapped to the internal a[18:11]. (internal a[18:0]) six-byte code for 3.3v-only software chip erase 5555 2aaa 5555 5555 2aaa 5555 a[10:0] #oe #we r/#c sector/page erase timing diagram sb2 sb1 sb0 a[10:0] dq[7:0] sb3 sb4 sb5 internal erase starts six-byte code for 3.3v-only sector/page erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa sa/pa aa 55 80 aa 55 30/50 sa = sector address and pa = page address, please ref. to the "table of command definition" note: the internal address a[18:0] are converted from external column/row address. column/row address are mapped to the low/high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[7:0] are mapped to the internal a[18:11]. (internal a[18:0]) #oe #we r/#c
w39v040a - 22 - 10. lpc interface mode ac characteristics ac test conditions parameter conditions input pulse levels 0.6 v dd to 0.2 v dd input rise/fall slew rate 1 v/ns input/output timing level 0.4 v dd / 0.4 v dd output load 1 ttl gate and c l = 10 pf read/write cycle timing parameters (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) w39v040a parameter symbol min. max. unit clock cycle time t cyc 30 - ns input set up time t su 7 - ns input hold time t hd 0 - ns clock to data valid t kq 2 11 ns note: minimum and maximum time has different l oads. please refer to pci specification. reset timing parameters parameter symbol min. typ. max. unit v dd stable to reset active t prst 1 - - ms clock stable to reset active t krst 100 - - s reset pulse width t rstp 100 - - ns reset active to output float t rstf - - 50 ns reset inactive to input active t rst 1 - - s note: all ac timing signals observe the following guide lines for determining setup and hold times: (a) high level signal's reference level is input high and (b) low level signal's reference level is input low. ref. to the ac testing condition.
w39v040a publication release date: december 19, 2002 - 23 - revision a2 11. timing waveforms for lpc interface mode read cycle timing diagram t cyc lad[3:0] start memory read cycle load address in 8 clocks clk 1 clock 1 clock tar next star t 1 clock 2 clocks 1 clock 010xb 0000b a[15:12] address sync tar 1111b tri-state 0000b t kq t hd t su a[11:8] a[7:4] a[3:0] data out 2 clocks d[7:4] data d[3:0] 0000b a[19:16] a[31:28] a[23:20] a[27:24] #lfram #reset write cycle timing diagram t cyc lad[3:0] start memory write cycle load address in 8 clocks clk 1 clock 1 clock tar next star t 1 clock 2 clocks 1 clock 011xb 0000b a[15:12] load data in 2 clocks d[7:4] address sync tar data 1111b tri-state 0000b t hd t su a[11:8] a[7:4] a[3:0] d[3:0] 0000b a[19:16] a[31:28] a[23:20] a[27:24] #lfram #reset
w39v040a - 24 - timing waveforms for lpc interface mode, continued program cycle timing diagram lad[3:0] 1st start memory write cycle load address "5555" in 8 clocks clk 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in lpc mode. 2nd start load address "2aaa" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in lpc mode. 3rd start load address "5555" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "a0" in 2 clocks 1010b 0000b write the 3rd command to the device in lpc mode. 4th start load ain in 8 clocks clk clk clk 1 clock 1 clock tar sync internal program start tar 1 clock 2 clocks 011xb 0000b a[15:12] load din in 2 clocks d[7:4] write the 4th command(target location to be programmed) to the device in lpc mode. a[11:8] a[7:4] a[3:0] d[3:0] 1111b tri-state 0000b data address address address address sync tar data sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b 1111b tri-state 0000b memory write cycle memory write cycle memory write cycle internal program start a[19:16] a[31:28] a[23:20] a[27:24] lad[3:0] lad[3:0] lad[3:0] #lfram #reset #lfram #reset #lfram #reset #lfram #reset
w39v040a publication release date: december 19, 2002 - 25 - revision a2 timing waveforms for lpc interface mode, continued #data polling timing diagram read the dq7 to see if the internal write complete or not. start memory read cycle load address in 8 clocks clk 1 clock 1 clock tar next start 1 clock 2 clocks 1 clock 010xb 0000b xxxxb xxxxb xxxxb xxan[17:16] an[15:12] address sync tar 1111b tri-state 0000b an[11:8] an[7:4] an[3:0] data out 2 clocks dn7,xxx data xxxxb 0000b start memory read cycle load address in 8 clocks clk 1 clock tar next start 1 clock 2 clocks 1 clock 010xb 0000b address sync tar 1111b tri-state 0000b data out 2 clocks data 0000b when internal write complete, the dq7 will equal to dn7. dn7,xxx xxxxb an[15:12] an[11:8] an[7:4] an[3:0] lad[3:0] 1st start load address "an" in 8 clocks clk 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b an[15:12] load data "dn" in 2 clocks dn[7:4] write the last command(program or erase) to the device in lpc mode. address sync tar data 1111b tri-state 0000b an[11:8] an[7:4] an[3:0] dn[3:0] memory write cycle 0000b 1 clock a[19:16] a[31:28] a[23:20] a[27:24] an[31:28] an[27:24] an[23:20] an[19:16] lad[3:0] lad[3:0] #lfram #reset #lfram #reset #lfram #reset
w39v040a - 26 - timing waveforms for lpc interface mode, continued toggle bit timing diagram read the dq6 to see if the internal write complete or not. lad[3:0] start memory read cycle load address in 8 clocks clk 1 clock 1 clock tar next start 1 clock 2 clocks 1 clock 010xb 0000b xxxxb xxxxb xxxxb address sync tar 1111b tri-state 0000b data out 2 clocks x,d6,xxb data xxxxb 0000b lad[3:0] start memory read cycle load address in 8 clocks clk 1 clock tar next start 1 clock 2 clocks 1 clock 010xb 0000b xxxxb xxxxb xxxxb address sync tar 1111b tri-state 0000b data out 2 clocks data 0000b when internal write complete, the dq6 will stop toggle. x,d6,xxb xxxxb lad[3:0] 1st start load address "an" in 8 clocks clk 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb an[15:12] load data "dn" in 2 clocks dn[7:4] write the last command(program or erase) to the device in lpc mode. address sync tar data 1111b tri-state 0000b an[11:8] an[7:4] an[3:0] dn[3:0] xxan[17:16] memory write cycle xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb 1 clock #lfram #reset #lfram #reset #lfram #reset
w39v040a publication release date: december 19, 2002 - 27 - revision a2 timing waveforms for lpc interface mode, continued boot block lockout enable timing diagram clk lad[3:0 ] 1st start load address "5555" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in lpc mode. address sync tar data 1111b tri-state 0000b memory write cycle clk 2nd start load address "2aaa" in 8 clocks 1 clock 1 clock tar start next command 1 clocks 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in lpc mode. address sync tar data 1111b tri-state 0000b memory write cycle lad[3:0 ] clk 3rd start load address "5555" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "80" in 2 clocks 1000b 0000b write the 3rd command to the device in lpc mode. address sync tar data 1111b tri-state 0000b memory write cycle lad[3:0 ] clk 4th start load address "5555" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 4th command to the device in lpc mode. address sync tar data 1111b tri-state 0000b memory write cycle lad[3:0 ] clk 5th start load address "2aaa" in 8 clocks 1 clock 1 clock tar 1 clock 2 clocks start next command 1 clock 011xb 0000b xxxxb xxxx xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 5th command to the device in lpc mode. address sync tar data 1111b tri-state 0000b memory write cycle lad[3:0 ] clk 6th start load address "5555" 8 clocks 1 clock 1 clock tar sync tar 1 clock 2 clocks 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101 b load data "40" or "70" in 2 clocks 0100b write the 6th command to the device in lpc mode. 0101 b 0101b 0101b 0000b 1111b tri-state 0000b data address memory write cycle 0111b lad[3:0 ] start next command 1 clock #lfram #reset #lfram #reset #lfram #reset #lfram #reset #lfram #reset #lfram #reset
w39v040a - 28 - timing waveforms for lpc interface mode, continued chip erase timing diagram 6th start load address "5555" in 8 clocks 1 clock 1 clock tar sync internal erase start tar 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b load data "10" in 2 clocks 0001b write the 6th command to the device in lpc mode. 0101b 0101b 0101b 0000b 1111b tri-state 0000b data address lad[3:0] 1st start clk tar start next command 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b 1010b 1010b lad[3:0] clk lad[3:0] clk lad[3:0] clk address sync tar data load address "5555" in 8 clocks 1 clock 1 clock 1 clock 2 clocks 1 clock load data "aa" in 2 clocks write the 1st command to the device in lpc mode. 2nd start load address "2aaa" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in lpc mode. 3rd start load address "5555" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "80" in 2 clocks 1000b 0000b write the 3rd command to the device in lpc mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b 1111b tri-state 0000b 4th start load address "5555" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 4th command to the device in lpc mode. 5th start load address "2aaa" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 5th command to the device in lpc mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b lad[3:0] clk lad[3:0] clk 2 clocks memory write cycle memory write cycle memory write cycle memory write cycle memory write cycle memory write cycle internal erase start #lfram #reset #lfram #reset #lfram #reset #lfram #reset #lfram #reset #lfram #reset
w39v040a publication release date: december 19, 2002 - 29 - revision a2 timing waveforms for lpc interface mode, continued sector erase timing diagram 6th start load sector address in 8 clocks 1 clock 1 clock tar sync internal erase start tar 1 clock 2 clocks 011xb 0000b xxxxb xxxxb xxxxb xxxxb sa[18:16] load data "30" in 2 clocks 0011b write the 6th command(target sector to be erased) to the device in lpc mode. 0000b 1111b tri-state 0000b data address 1st start load address "5555" in 8 clocks clk 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in lpc mode. clk clk clk address sync tar data 2nd start load address "2aaa" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in lpc mode. 3rd start load address "5555" in 8 clocks 1 clocks 1 clocks tar start next command 1 clocks 2 clocks 1 clocks 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "80" in 2 clocks 1000b 0000b write the 3rd command to the device in lpc mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b 1111b tri-state 0000b 4th start memory write cycle load address "5555" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 4th command to the device in lpc mode. 5th start load address "2aaa" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 5th command to the device in lpc mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b clk clk xxxxb xxxxb xxxxb memory write cycle memory write cycle memory write cycle memory write cycle memory write cycle internal erase start lad[3:0] lad[3:0] lad[3:0] lad[3:0] lad[3:0] lad[3:0] #lfram #reset #lfram #reset #lfram #reset #lfram #reset #lfram #reset #lfram #reset
w39v040a - 30 - timing waveforms for lpc interface mode, continued page erase timing diagram 6th start load page address in 8 clocks 1 clock 1 clock tar sync internal erase start tar 1 clock 2 clocks 011xb 0000b xxxxb xxxxb xxxxb pa[15:12] load data "50" in 2 clocks 0101b write the 6th command(target page to be erased) to the device in lpc mode. 0000b 1111b tri-state 0000b data address 1st start load address "5555" in 8 clocks clk 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in lpc mode. clk clk clk address sync tar data 2nd start load address "2aaa" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in lpc mode. 3rd start load address "5555" in 8 clocks 1 clocks 1 clocks tar start next command 1 clocks 2 clocks 1 clocks 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "80" in 2 clocks 1000b 0000b write the 3rd command to the device in lpc mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b 1111b tri-state 0000b 4th start memory write cycle load address "5555" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 4th command to the device in lpc mode. 5th start load address "2aaa" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 5th command to the device in lpc mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b clk lad[3:0] clk xxxxb xxxxb xxxxb memory write cycle memory write cycle memory write cycle memory write cycle memory write cycle internal erase start pa[18:16] lad[3:0] lad[3:0] lad[3:0] lad[3:0] lad[3:0] #lfram #reset #lfram #reset #lfram #reset #lfram #reset #lfram #reset #lfram #reset
w39v040a publication release date: december 19, 2002 - 31 - revision a2 timing waveforms for lpc interface mode, continued gpi register readout timing diagram note: read the dq[4:0] to capture the states(high or low) of the gpi[4:0] input pins. the dq[7:5] are reserved bits. lad[3:0] start memory read cycle load address "ffbxe100(hex)" in 8 clocks clk 1 clock 1 clock tar next start 1 clock 2 clocks 1 clock 010xb 0000b 1111b address sync tar 1111b tri-state 0000b data out 2 clocks d[7:4] data 0000b 1111b 1011b xxxxb 1110b 0001b 0000b 0000b d[3:0] #lfram #reset reset timing diagram clk vdd lad[3:0] t prst t krst t rstp t rst f t rst #lfram #reset
w39v040a - 32 - 12. ordering information part no. access time (ns) power supply current max. (ma) standby v dd current max. (ma) package W39V040AP 11 20 10 32l plcc w39v040aq 11 20 10 32l stsop notes: 1. winbond reserves the right to make c hanges to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 13. how to read the top marking example: the top marking of 32-pin stsop w39v040aq 1 st line: winbond logo 2 nd line: the part number: w39v040aq 3 rd line: the lot number 4 th line: the tracking code: 149 o b sa 149: packages made in '01, week 49 o: assembly house id: a means ase, o means ose, ... etc. b: ic revision; a means version a, b means version b, ... etc. sa: process code w39v040aq 2138977a-a12 149obsa
w39v040a publication release date: december 19, 2002 - 33 - revision a2 14. package dimensions 32l plcc notes: l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusi o 3. controlling dimension: inches 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.95 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.490 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.510 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 32l stsop min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 0.50 0.00 0 0.22 0.27 ----- 0.21 12.40 8.00 14.00 0.50 0.60 0.70 0.80 0.10 35 0.047 0.006 0.041 0.040 0.035 0.007 0.009 0.010 0.004 ----- 0.008 0.488 0.315 0.551 0.020 0.020 0.024 0.028 0.031 0.000 0.004 035 0.002 a a b c d e e l l y 1 1 2 a h d dimension in mm a a a 2 1 l l 1 y e h d d c b e
w39v040a - 34 - 15. version history version date page description a1 october 8, 2002 - initial issued a2 dec. 19, 2002 14 modify pgm mode power supply current (icc) parameter from 20 ma (typ.) to 10 ma (typ.) and 30 ma (max.) to 20 ma (max.) 1, 15, 32 modify lpc mode power supply current (icc) parameter from 40 ma (typ.) to 12.5 ma (typ.) and 60 ma (max.) to 20 ma (max.) 15 modify cmos standby current (isb1) parameter from 20 a (typ.) to 5 a (typ.) and 100 a (max.) to 25 a (max.) headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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